1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming a nanowire device with a gate-all-around-channel configuration, and the resulting semiconductor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by setting the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. To improve the operating speed of conventional FETs, device designers have significantly reduced the channel length of such devices, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also makes it difficult to control the channel region of the device. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes a plurality of trenches 14 that define three illustrative fins 16, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. The fins 16 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L of the fins 16 corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 16 covered by the gate structure 18 are the channel regions of the FinFET device 10. The gate structure 18 is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode (not separately shown) for the device 10.
Another known transistor device is typically referred to as a nanowire device. In a nanowire device, at least the channel region of the device is comprised of one or more very small diameter, wire-like semiconductor structures. As with the other types of transistor devices discussed above, current flow through a nanowire device is controlled by setting the voltage applied to the gate electrode. When an appropriate voltage is applied to the gate electrode, the channel region of the nanowire device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region, i.e., current flows through the nanowire structure. Persons skilled in the art will recognize that there are various known techniques that may be employed to manufacture such nanowire devices. Accordingly, the processing details for forming a basic nanowire device structure will not be described in detail herein.
As device dimensions have decreased, it is becoming ever more challenging to maintain adequate control of the channel region of transistor devices during operation. Device designers have used various techniques to insure that there is adequate capacitive coupling between the gate electrode of the device and the channel region of the device during operation. Absent proper capacitive coupling, control of the channel region is difficult and may result in devices having less desirable electrical performance capabilities. In the case of nanowire devices, device designers have such devices wherein the gate electrode and gate insulation layer surround the nanowire structure in an effort to obtain better control of the channel region.
The present disclosure is directed to various methods of forming a nanowire device or a Fin-type device with a gate-all-around-channel configuration, and the resulting semiconductor device, that may reduce or eliminate one or more of the problems identified above.